For a variety of integrated circuit devices, a clock generator is indispensable for providing clock signals to actuate the operation of an integrated circuit devices. For some integrated circuits (or ICs) involved in specific technical applications, for example, the Gigabit Ethernet Serdes IC, a high-frequency clock generator is essential to the IC for providing high-frequency clock signals to drive the IC to work at a high frequency.
Referring to FIG. 1, a feasible high-frequency clock generator of the prior art is made up of a single phase-locked loop (PLL)1. The axioms for the phase-locked loop 1 to generate high-frequency clock signals is on the basis of enabling the voltage-controlled oscillator (VCO) thereof to oscillate directly at a desired high frequency to output high-frequency clock signals. As is well known in the related art, the phase-locked loop 1 utilizes a negative feedback loop to generate an output oscillating clock signal in synchronization with the phase/frequency of the input clock signal, and an output voltage Vo proportional to the variation of the input clock frequency. As illustrated in FIG. 1, the phase-locked loop 1 includes a phase/frequency detector 11, a charge pump 12, a low-pass filter 13, a voltage-controlled oscillator 14 and a frequency divider 15. The phase-locked loop 1 is configured to generate an output clock signal of a frequency fVCO being N times as the input clock frequency fi, and the phase θVCO of the output clock signal fVCO is kept in synchronization with the phase θi of the input clock signal fi. However, if the PLL 1 is configured to directly oscillate at a high frequency to output high-frequency clock signals, the voltage-controlled oscillator 14 will consume considerable power. And what is worse, because the power consumption of the VCO 14 is approximately proportional to the square of its operating frequency, as the operating frequency of the VCO 14 rises, the power consumption of the whole PLL 1 will grow up approximately in an exponential fashion. Therefore, the prior art of using a single PLL as a high-frequency clock generator is a quite power-consuming practice.
FIG. 2 shows the circuit configuration of another high-frequency clock generator according to the prior art. In FIG. 2, the clock generator 2 includes a PLL 21, a delayed lock loop (DLL) 22 and a logic circuit 23. The way of generating high-frequency clock signals by the clock generator of FIG. 2 depends on the PLL 21 to generate low-frequency clock signals fL and the DLL 22 to impose phase delays on the low-frequency clock signals fL to generate multiple low-frequency clock signals with a constant phase difference (f1, f2, . . . ). The logic circuit 23 receives the multiple low-frequency clock signals (f1, f2, . . . ) and outputs high-frequency clock signals fH in the control of the control signal fCTRL. Comparing the high-frequency clock generator of FIG. 2 with that of FIG. 1, the circuit topology of the high-frequency clock generator of FIG. 2 though does not require the PLL 21 to work at a high frequency, a DLL 22 is additionally required and a control signal fCTRL is needed for switching the logic states of the logic circuit 23. Further, the relationships among the parameters of the control signal fCTRL and of the multiple low-frequency clock signals (f1, f2, . . . ), for example, skew, duty cycle, setup time, hold time, etc., are difficult to control, and the relationships among the clock signals in the DLL 22 are somewhat difficult to handle.
It is inclined to look for a high-frequency clock generator with low power consumption, which can receive a low-frequency input clock signal and outputs a high-frequency clock signal of a frequency being N×2n times as the input clock frequency.